Modeling and Comparative Analysis of Logic Gates for Adder and Multiplier Applications -A VLSI based approach

The logic gates are the fundamental building blocks of VLSI and embedded applications. These gates can be designed using several design techniques and implemented at different levels of architectures. This paper focuses on design and evaluate the performance of logic gates used in the Adders and Multiplier using various design technique like CMOS design GDI design and PTL design. These different design styles have pros and corns with reference to performance measure as Delay, Power consumption, Area and Gate Count. The design and simulation of logic gates is performed on CADENCE Design Suit 6.1.6 using Virtuoso and ADE Environment at GPDK 180nm technology. Comparative study between logic gates designed using CMOS, GDI and Degenerated PTL technique is presented in this paper, with performance measure as Number of transistor (Gate count), Power, Delay, Area and Power Delay Product.